1. Field of the Invention
The present invention relates generally to digital pixel sensor architecture and, more particularly, to complementary metal oxide semiconductor (CMOS) image sensor systems with self-reset digital pixel sensor architecture for improving signal-to-noise ratio (SNR) and extending dynamic range thereof.
2. Description of the Related Art
An image sensor converts an optical image focused on the sensor into electrical signals. The electrical signals represent the intensity of the image. Replacing earlier vidicon tube type image sensing devices, charge-coupled device (CCD) image sensors have become the core technology of modern imaging devices such as digital cameras.
CCD sensors have many strengths, including small size, high sensitivity, and high fill factor. However, CCD sensors also have many weaknesses, including limited readout rates and limited dynamic range. The most well known weakness is the difficulty and high costs of integrating CCD image sensors with CMOS-based microprocessors. CMOS-based integrated circuit (IC) chips containing a CCD image sensor usually have a relatively low yield and are quite expensive because of the specialized processing involved.
CCD image sensors are well known in the art and thus are not described herein. An exemplary teaching can be found in U.S. Pat. No. 5,272,535, which is incorporated herein by reference, titled “Image Sensor with Exposure Control, Selectable Interlaced, Pseudo Interlaced or Non-Interlaced Readout and Video Compression”, issued to Elabd of Sunnyvale, Calif., and assigned to Loral Fairchild Corporation, Syosset, N.Y., December 1993.
The CMOS technology provides the possibility of integrating image sensing and digital signal processing on the same chip, which has been widely accepted as the main advantage over CCD image sensors. The CMOS image sensors have the potential of replacing the CCD image sensors, just as CCD image sensors replaced the vidicon tube image sensing devices.
The current CMOS technology offers smaller, less expensive, and lower power image sensing devices. The advantages of CMOS image sensors over CCD image sensors are well known. An exemplary teaching, which is incorporated herein by reference, can be found in “Technology and Device Scaling Considerations for CMOS Imagers”, IEEE Transactions on Electron Devices, Vol. 43, No. 12, December 1996, disclosing several advantages of CMOS image sensors, including:                1) Low-voltage operation and low power consumption;        2) Compatibility with on-chip electronics integration (control logic and timing, image processing, and signal-conditioning such as analog-to-digital (A/D) conversion);        3) Random access of image data; and        4) Potentially lower cost as compared to conventional CCD image sensors.        
Current CMOS image sensors come in several different types of pixel architectures, such as the passive pixel sensor (PPS) architecture, the active pixel sensor (APS) architecture, and the recently introduced digital pixel sensor (DPS) architecture.
PPS and APS are well known in the art and thus are not described herein. Exemplary teachings, which are incorporated herein by reference, can be found in U.S. Pat. No. 5,841,126, titled “CMOS Active Pixel Sensor Type Imaging System on A Chip”, issued to Fossum et al. of California and assigned to California Institute of Technology, November 1998, and “CMOS Active Pixel Image Sensors Fabricated Using a 1.8-V, 0.25-μm CMOS Technology”, IEEE Transactions on Electron Devices, Vol. 45, No. 4, April 1998, by Wong et al.
The digital pixel sensor incorporates A/D conversion at the pixel level. It is known in the art that A/D conversion can be integrated at the chip level, at the column level, or at the pixel level. The chip level approach is so far the most commonly used, wherein a single conventional high-speed analog-to-digital converter (ADC) is integrated with an image sensor.
To lower the ADC operating speed, the column level approach is used. In this case, an array of ADC's, each dedicated to one or more columns of the sensor array, is employed. The ADC's are operated in parallel, and, therefore, low-to-medium-speed ADC architectures can be employed.
To lower the ADC speeds even further, the pixel level digitization is used. In this approach, an ADC is dedicated for each pixel or each group of neighboring pixels and the ADC's are operated in parallel.
Exemplary teachings on CMOS image sensor architectures employing different approaches, including the pixel level A/D conversion approach, can be found in the following publications, which are all hereby incorporated herein by reference:    1. U.S. Pat. No. 5,461,425, titled “CMOS Image Sensor with Pixel Level A/D Conversion”, issued to Fowler et al. and assigned to Stanford University in Palo Alto, Calif., October 1995.    2. David Yang, Boyd Fowler, and Abbas El Gamal, “A 128×128 Pixel CMOS Area Image Sensor with Multiplexed Pixel Level A/D conversion”, IEEE CICC96, 1996.    3. Boyd Fowler, Abbas El Gamal, and David Yang, “Techniques for Pixel Level analog to Digital Conversion”, SPIE, Infrared Readout Electronics IV, Proceedings, Vol. 3360, pp. 2-12, April 1998.    4. U.S. Pat. No. 5,801,657, titled “Serial analog-to-Digital Converter Using Successive Comparisons”, issued to Fowler et al. and assigned to Stanford University in Palo Alto, Calif., September 1998.    5. U.S. Pat. No. 5,818,052, titled “Low Light Level Solid State Image Sensor”, issued to Elabd of Sunnyvale, Calif., and assigned to Loral Fairchild Corp., Syosset, N.Y., October 1998.    6. U.S. Pat. No. 5,844,514, titled “Analog-to-Digital Converter And Sensor Device Comprising Such A Converter”, issued to Ringh et al. and assigned to Forsvarets Forskningsanstalt in Stockholm, Sweden, December 1998.    7. Abbas El Gamal, David Yang, and Boyd Fowler, “Pixel Level Processing—Why, What, and How?”, SPIE Electronic Imaging '99 Conference, Proceedings, Vol. 3650, January 1999.    8. Woodward Yang et al., “An Integrated 800×600 CMOS Imaging System”, IEEE ISSCC99, Session 17, WA 17.3, February 1999.    9. David Yang, Abbas El Gamal, Boyd Fowler, and Hui Tian, “A 640×512 CMOS Image Sensor with Ultra Wide Dynamic Range Floating-Point Pixel-Level ADC”, IEEE ISSCC99, Session 17, WA 17.5, February 1999.    10. David Yang, Boyd Fowler, and Abbas El Gamal, “A Nyquist-Rate Pixel-Level ADC for CMOS Image Sensors”, IEEE J. of Solid-State Cir., Vol. 34, No. 3, March 1999.    11. Stuart Kleinfelder, Suk Hwan Lim, Xinqiao Liu, and Abbas El Gamal, “A 10,000 Frames/s 0.18 μm CMOS Digital Pixel Sensor with Pixel-Level Memory”, 2001 IEEE Int. Solid-State Cir. Conf., proceedings, February 2001.
As known in the art and described in these publications, the DPS architecture having pixel level A/D conversion offers the potential of achieving the highest SNR and the lowest power consumption since it is performed in parallel, close to where the signals are generated, and can be operated at very low speeds.
In addition, the DPS architecture offers better scaling with CMOS technology due to reduced analog circuit performance demands and the elimination of column fixed-pattern noise (FPN) and column readout noise. In addition, the same pixel and ADC design and layout can be readily used for a very wide range of sensor sizes. The non-destructive, high frame rate advantages of DPS benefit traditional high speed imaging applications and enabling new imaging enhancement capabilities such as multiple sampling for increasing sensor dynamic range.
However, pixel level A/D conversion implementations must meet stringent area and power requirements. For example, as described in above-referenced article, “A 10,000 Frames/s 0.18 μm CMOS Digital Pixel Sensor with Pixel-Level Memory”, achieving acceptable pixel sizes using DPS architecture requires the use of a 0.18 μm or smaller CMOS process, which is challenging due to reduced supply voltages and increased leakage currents.
As a result, most CMOS image sensor systems currently available on the market employ an APS architecture that is implemented with chip or column level ADC's.
Unfortunately, CMOS APS image sensors are usually noisier than CCD image sensors. In other words, CMOS APS image sensors generally suffer from limited dynamic range and poor SNR, limiting their use in most image sensor and higher-end video applications. This noise can be reduced but it takes extra processing power, which in turn requires more parts or a more complex IC—negating the reason for using CMOS image sensor in the first place.
To overcome the problem of limited dynamic range in CMOS APS image sensors, a self reset pixel architecture has been proposed in U.S. Pat. No. 6,130,713, issued to Merrill of Woodside, Calif., and assigned to Foveonics, Inc., in Cupertino, Calif.
In Merrill, the dynamic range of a conventional CMOS APS cell is extended. This is achieved by adding circuitry to the convention CMOS APS cell, enabling it to repeatedly reset itself and store the number of times the APS cell has been reset.
The dynamic range of an APS cell is commonly defined by the ratio of the maximum number of photons that the cell can collect during an integration period without saturation, i.e., without exceeding the physical well capacity of the APS cell, and a minimum number of photons that the APS cell can collect during the integration period that can be detected over the noise floor.
To improve the dynamic range, Merrill proposed the following. During an integration period a transistor functioning as a comparator compares the voltage level of an APS cell with a reference voltage. Once the voltage level of the APS cell exceeds the reference voltage level, a reset circuit resets the APS cell's photodiode. After each reset, a reset value is stored in a memory circuit. The sum of the reset values stored in the memory circuit corresponds to the number of times the APS cell has been reset.
FIG. 1 shows a schematic drawing of a prior art self reset APS architecture wherein an image cell 100 includes a photodiode D1; a reset transistor T9; a level shifter between voltage supply VDD1 and reference voltage supply VDD2, formed by transistors T10-T12; a first inverter circuit IV1; a second inverter circuit IV2; and analog memory circuit 103 formed by transistor T6 and capacitor C1; and source follower transistors T13, T14 and select transistors T16, T15 which provide information to respective high and low order bit information lines 101, 102.
In this prior art architecture, an image integration of the image cell 100 begins with an application of a reset voltage VRT from node N2 to the gate of reset transistor T9. After reset, the image cell 100 is then read to obtain a reset value that represents the initial integration voltage on photodiode D1 less a threshold voltage drop of buffer transistor T13.
Once the initial reset value is obtained, the integration voltage on Dl increases with time during the integration period. When the circuitry in image cell 100 senses that the integration voltage is approaching the saturation level of the image cell 100, the reset transistor T9 resets the image cell 100 to begin a second integration period.
The image cell 100 determines when the integration voltage of image cell 100 is approaching the saturation level by comparing the integration voltage with a reference voltage. Once the integration voltage exceeds the reference voltage, transistor T9 resets the image cell 100. The image cell 100 can be reset many times. The number of times the image cell 100 has been reset is stored in memory circuit 103.
This prior art self reset APS sensor architecture suffers from the following drawbacks:    1. There is no reset mechanism for the analog memory circuit 103. Specifically, there is no mechanism to reset capacitor C1 of the analog memory circuit 103 when continuous operation is required.
The analog memory circuit 103 keeps track of the number of times the image cell 100 has been reset by storing a unit of charge on the capacitor C1 every time a reset is executed. Without a reset mechanism, the capacitor C1 will saturate in video applications that require the image cell to work continuously. When the capacitor C1 is saturated, the analog memory circuit 103 will not be able to count the number of self-reset.    2. One saturated active pixel cell may trigger undesirable reset of an entire array of active pixel cells.
As described above and with reference to FIG. 1, the active pixel cell, i.e., the image cell 100, begins cell integration with an application of a reset voltage VRT from node N2 to the gate of reset transistor T9. After reset, the image cell 100 is then read to obtain a reset value that represents the initial integration voltage on photodiode D1 less a threshold voltage drop of buffer transistor T13.
In other words, each active pixel cell is first reset and then read to obtain an initial reset value. This indicates that every active pixel cell begins integration with a global reset signal being applied to each active pixel cell's N2 node. As such, this global reset would connect an array of active pixel cells together. In essence, every node N2 in each of the active pixel cells in the array is connected to one another via the global reset.
After the first reset and during integration, when one image cell approaches saturation, its self reset circuit generates a high voltage signal, i.e., a reset signal, on the same node N2 to reset its own photodiode. Since all active pixel cells' N2 nodes are connected together via the global reset, this means that, when one of them resets, it would also trigger the entire array of active pixel cells to be reset accordingly. This is not desirable.    3. The reference voltage supply circuit VDD2 is unstable and thus may trigger false self-reset.
As shown in FIG. 1, both inverters, IV1 and IV2, are connected to the reference voltage supply circuit VDD2. When the first inverter circuit IV1, consisting of PMOS transistor T2 and NMOS transistor T5, is turned on, it outputs a low voltage signal at node N4. In turn, the second inverter circuit, consisting of PMOS transistor T3 and NMOS transistor T6, outputs a high voltage signal at node N2. This high voltage signal is the reset voltage VRT that turns on the reset transistor T9.
Since the reference voltage supply circuit VDD2 is closely connected to both inverter circuits IV1 and IV2, each time an inverter switching occurs, the reference voltage supply circuit VDD2 is inevitably disturbed. Because the reference voltage supply circuit VDD2 is affected by inverter switching and thus unstable, false self reset may be triggered.    4. By adding circuitry to a conventional active pixel cell, this prior art self reset APS architecture provides an undesirably large active pixel cell that still suffers from poor SNR and other drawbacks commonly found in CMOS APS implementations.